1. Field of the Invention
The present invention relates to a large scale integrated semiconductor memory, and more particularly, it relates to a dynamic random access memory (referred to as a dynamic RAM hereinafter) formed by CMOS process.
2. Description of the Prior Art
A dynamic RAM generally employs a memory cell comprising a single transistor and a single capacitor. In this case, the smaller the ratio of capacitance of a bit line to capacitance of a capacitor in a memory cell is, the larger amount of change in potential on a bit line at the time of read-out is, and correspondingly the larger input potential difference for a sense amplifier is, so that read-out operation of information is ensured. However, as memory capacity is largely increased and integration thereof increases, the size of a memory cell becomes smaller, so that capacitance of a memory cell is reduced. On the other hand, since the number of memory cells connected to a single bit line increases, a bit line becomes longer, so that capacitance of a bit line tends to increase. As a result, the ratio of capacitance of a bit line to capacitance of a memory cell increases, so that read-cut operation of information may not be ensured. To solve this problem, a single bit line is divided into a plurality of blocks so that the ratio of capacitance of a memory cell and a capacitance of a bit line may be reduced.
FIG. 1 is a circuit diagram showing a structure of a part of a conventional dynamic RAM, which is disclosed in, for example, an article by R. I. Kung et al., entitled "A Sub 100 ns 256 K DRAM in CMOS III Technology", Digest of Technical Papers, ISSCC 84, pp. 278-279. The structure of this circuit is now described. In FIG. 1, a so-called shared sense amplifier structure is shown wherein a bit line is divided into two parts and a sense amplifier is shared with the divided bit lines on both sides. In the above described document, a transistor in a memory cell comprises a p channel MOS transistor, a sense amplifier comprises a p channel MOS transistor, and a restore circuit comprises an n channel MOS transistor. For simplicity of illustration, these transistors have a conductivity type opposite to the above described conductivity type, in FIG. 1. In addition, the structure of the circuit is slightly simplified, so that only a pair of folded bit lines out of a plurality of pairs of folded bit lines is shown.
A pair of folded bit lines are divided into divided bit lines BL1, BLN, BL2, BL1, BLN and BL2. The divided bit lines BLN and BLN are paired and connected to a sense amplifier SA for discharging the bit line at a low potential to a ground potential. The divided bit lines BL1 and BL1 are paired and connected to a restore circuit RE1 for charging the bit line at a high potential to a power supply potential. The divided bit lines BL2 and BL2 are paired and connected to a restore circuit RE2 for charging the bit line at a high potential to the power supply potential.
The sense amplifier SA comprises an n channel MOS transistor QN1 having a drain connected to the divided bit line BLN, a gate connected to the divided bit line BLN and a source connected to one conduction terminal of a sense amplifier driver transistor QN5, and an n channel MOS transistor QN2 having a drain connected to the divided bit line BLN, a gate connected to the divided bit line BLN and a source connected to one conduction terminal of the sense amplifier driver transistor QN5. The sense amplifier driver transistor QN5 is turned on in response to a sense amplifier activating signal applied to the gate thereof, so that a ground potential V.sub.SS is transferred to the sources of the transistors QN1 and QN2.
The restore circuit RE1 comprises a p channel MOS transistor QP1 having a drain connected to the divided bit line BL1, a gate connected to the divided bit line BL1 and a source connected to one conduction terminal of a restore circuit driver transistor QP5, and a p channel MOS transistor QP2 having a drain connected to the divided bit line BL1, a gate connected to the divided bit line BL1 and a source connected to one conduction terminal of the restore circuit driver transistor QP5. The restore circuit driver transistor QP5 is turned on in response to a restore circuit activating signal SP1 applied to the gate thereof, so that a power supply potential V.sub.CC is transferred to the sources of the transistors QP1 and QP2.
The restore circuit RE2 comprises a p channel MOS transistor QP3 having a drain connected to the divided bit line BL2, a gate connected to the divided bit line BL2 and a source connected to one conduction terminal of a restore circuit driver transistor QP6, and a p channel MOS transistor QP4 having a drain connected to the divided bit line BL2, a gate connected to the divided bit line BL2 and a source connected to one conduction terminal of the restore circuit driver transistor QP6. The restore circuit driver transistor QP6 is turned on in response to a restore circuit activating signal SP2, so that the power supply potential V.sub.CC is transferred to the sources of the transistors QP3 and QP4.
The divided bit lines BL1 and BLN are connected to each other through a transfer gate QT1 formed of an n channel MOS transistor, and the divided bit lines BL1 and BLN are connected to each other through a transfer gate QT2 formed of an n channel MOS transistor. The transfer gates QT1 and QT2 are turned on in response to a transfer signal T1.
The divided bit lines BLN and BL2 are connected to each other through a transfer gate QT3 formed of an n channel MOS transistor. The divided bit lines BLN and BL2 are connected to each other through a transfer gate QT4 formed of an n channel MOS transistor. The transfer gates QT3 and QT4 are turned on in response to a transfer signal T2.
The divided bit line BL1 and a bus line BU for transferring data are connected to each other through a column gate transistor QY1 formed of an n channel MOS transistor. The divided bit line BL1 and a bus line BU for transferring data are connected to each other through a column gate transistor QY2 formed of an n channel MOS transistor. The column gate transistors QY1 and QY2 are turned on in response to a column selecting signal Y.
Although memory cells, the number of which depends on a memory capacity, are connected to each of the divided bit lines, only a memory cell MC1 connected to the divided bit line BL2 is typically shown. The memory cell MC1 comprises an n channel MOS transistor QS and a capacitor CS. The transistor QS has a gate being a part of a word line WL1 and a source connected to the divided bit line BL2. The capacitor CS has one electrode connected to the drain of the transistor QS and other electrode connected to a memory cell plate potential V.sub.SG.
FIG. 2 is a waveform diagram for explaining operation at the time of read-out of information stored in the memory shown in FIG. 1. Referring now to FIG. 2 which is a waveform diagram explaining operation of the circuit shown in FIG. 1, how information is read out is described when the capacitor CS in the memory cell MC1 is not charged, that is, when information "0" is stored.
At the time t.sub.0, the transfer signal T1 becomes an "L" level. Accordingly, the divided bit lines BLN and BL1 are isolated from each other and the divided bit lines BLN and BL1 are isolated from each other. By that time, the divided bit lines BL1, BL1, BL2, BL2, BLN and BLN have been precharged at an intermediate potential level (V.sub.CC -V.sub.SS)/2, where V.sub.CC is a power supply potential and V.sub.SS is a ground potential.
At the time t.sub.1, the potential on the selected word line WL1 becomes an "H" level. Accordingly, MOS transistor QS is turned on. As a result, the potential on the divided bit line BL2 slightly falls, so that potential difference occurs between the divided bit lines BL2 and BL2.
At the time t.sub.2, a sense amplifier activating signal SN becomes an "H" level. As a result, potential difference is increased between the divided bit lines BL2 and BL2. More specifically, the potential on the divided bit line BL2 is held near the above described intermediate potential, while the divided bit line BL2 is discharged through the transfer gate transistor QT3 and the sense amplifier SA, so that the potential thereon becomes near the ground potential V.sub.SS.
At the time t.sub.3, the restore circuit activating signal SP2 becomes an "L" level. As a result, the potential on the divided bit line BL2 is pulled up near the power supply potential V.sub.CC by the restore circuit RE2, so that potential difference is further increased between the divided bit lines BL2 and BL2.
At the time t.sub.4, the transfer signal T1 becomes again an "H" level. Thus, the potential on the divided bit lines BLN and BLN are transferred to the divided bit lines BL1 and BL1. As a result, the divided bit line BL1 is discharged, so that the potential thereon becomes near the ground potential V.sub.SS, while the potential on the divided bit line is pulled up.
At the time t.sub.5, the restore circuit activating signal SP1 becomes an "L" level. As a result, the potential on the divided bit line BL1 is pulled up near the power supply potential V.sub.CC.
At the time t.sub.6, the column selecting signal Y becomes an "H" level. Thus, the potential on the divided bit lines BL1 and BL1 are transferred to the bus lines BU and BU, so that information "0" stored in the memory cell MC1 is read out.
In the circuit shown in FIG. 1, information stored in the capacitor CS in the memory cell MC1 is read out to the divided bit line BL2, so that potential difference between the divided bit lines BL2 and BL2 is amplified by the sense amplifier SA. At that time, the divided bit line BL2 is discharged at the sense amplifier SA through a transfer gate transistor QT3. In a dynamic RAM with a folded bit line structure, a bit line is generally formed of a low resistive material such as aluminum or refractory metal siliside. Therefore, resistance of a bit line can be reduced, so that discharge of charges on the bit line can be accelerated. However, in a dynamic RAM with a shared sense amplifier structure, a transfer gate transistor is provided between a divided bit line connected to a memory cell and a sense amplifier, so that a bit line can not be formed of a low resistive material in this transfer gate transistor portion. In addition, as shown in FIG. 1, since the transfer gate transistor must be provided for each pitch between bit lines, the transistor width can be made almost the same as or at most twice the pitch between bit lines. Since the pitch between the bit lines is, for example, about 3 .mu.m in a 1 Mega-bit dynamic RAM, the transistor width of the transfer gate transistor is limited to less than several .mu.m. As a result, conductance of the transfer gate transistor is reduced, so that discharge of charges on the divided bit line is delayed when the sense amplifier operates. Furthermore, since a source and a drain of the transfer gate transistor are formed of a diffusion layer provided in a substrate or a well, noise is transferred to a bit line through the substrate or the well, so that the sense amplifier erroneously operates.
FIG. 3 is a circuit diagram showing a part of a structure of another conventional dynamic RAM, which is disclosed in the Japanese Laying-Open Gazette No. 101093/1984. The structure of this circuit is now described. In FIG. 3, the circuit comprises only n channel MOS transistors. For simplicity of illustration, only a pair of folded bit lines out of a plurality of pairs of folded bit lines, are shown herein.
The pair of folded bit lines are divided into three pairs of divided bit lines BL4 and BL4, BL5 and BL5 and BL6 and BL6. The pair of divided bit lines BL4 and BL4 are connected to an active pull-up circuit AP which is activated in response to an active pull-up signal APE for boosting the potential on the bit line at a high potential to the power supply potential, and a bit line precharge circuit BC for precharging the potential on the bit line to the intermediate potential.
The pair of divided bit lines BL5 and BL5 are connected to a sense amplifier SA5 which is activated in response to a sense amplifier driver signal for further increasing potential difference between the pair of divided bit lines.
The pair of divided bit lines BL6 and BL6 are connected to a sense amplifier SA6 which is activated in response to the sense amplifier driver signal for further increasing potential difference between the pair of divided bit lines.
The divided bit lines BL4 and BL5 are connected to each other through the transfer gate transistor QT1, while the divided bit lines BL4 and BL5 and are connected to each other through the transfer gate transistor QT2. The transfer gate transistors QT1 and QT2 are turned on in response to a transfer signal BSC.
The divided bit lines BL5 and BL6 are connected to each other through the transfer gate transistor QT3, while the divided bit lines BL5 and BL6 are connected to each other through the transfer gate QT4. The transfer gates QT3 and QT4 are turned on in response to the transfer signal BSC.
The divided bit line BL4 and the bus line BU for transferring data are connected to each other through the column gate transistor QY1, while the divided bit line BL and the bus line BU for transferring data are connected to each other through the column gate transistor QY2. The column gate transistors QY1 and QY2 are turned on in response to a column selecting signal.
Although memory cells, the number of which depends on a memory capacity, are connected to the divided bit lines BL5, BL5, BL6 and BL6 only a memory cell MC1 connected to the divided bit line BL5 is typically shown. The memory cell MC1 comprises the transfer transistor QS and the capacitor CS. The transistor QS has a gate being a part of the word line WL1. The capacitor CS has one electrode connected to the memory cell plate potential V.sub.SG.
FIG. 4 is a waveform diagram explaining operation at the time of read-out of information stored in the circuit shown in FIG. 3.
Referring now to FIG. 4 which is a waveform diagram explaining operation of the circuit shown in FIG. 3, how information is read out is described when the capacitor CS in the memory cell MC1 is not charged, that is, when information "0" is stored.
Before the time t.sub.0, the transfer signal BSC and a reset signal RST become an "H" level. Accordingly, all the transfer gate transistors QT1 to QT4 are turned on. Thus, the divided bit lines BL4, BL5 and BL6 are connected to each other, while the divided bit lines BL4, BL5 and BL6 are connected to each other. In addition, since the reset signal RST becomes an "H" level, the bit line precharge circuit BC operates, so that each of the divided bit lines is precharged, so that the potential thereon becomes the intermediate potential (V.sub.CC -V.sub.SS)/2.
At the time t.sub.1, both the transfer signal BSC and the reset signal RST become an "L" level, and the selected word line WL1 becomes an "H" level. As a result, the potential on the divided bit line BL5 slightly falls, so that potential difference occurs between the divided bit lines BL5 and BL5.
At the time t.sub.2, a sense amplifier activating signal SN5 becomes an "H" level. Accordingly, the sense amplifier SA5 is activated. As a result, potential difference is increased between the divided bit lines BL5 and BL5.
At the time t.sub.3, the transfer signal BSC becomes an "H" level. Accordingly, the transfer gate transistors QT1 to QT4 are turned on. As a result, the potentials on the divided bit lines BL5 and BL5 are transferred to the divided bit lines BL4 and BL6 and BL4 and BL6, respectively.
At the time t.sub.4, a sense amplifier activating signal SN6 becomes an "H" level. As a result, potential difference is increased between the divided bit lines BL6 and BL6, so that potential difference is increased between the divided bit lines BL4 and BL4 and between the divided bit lines BL5 and BL5.
At the time t.sub.5, the active pull-up signal APE becomes an "H" level. Accordingly, the active pull-up circuit AP operates. As a result, the potential on the divided bit lines BL4, BL5 and BL6 is pulled up near the power supply potential V.sub.CC. Then, the column selecting signal Y becomes an "H" level. Thus, the potential on the divided bit lines BL4 and BL4 are transferred to the bus lines BU and BU, so that information "0" stored in the memory cell MC1 is read out.
In the circuit shown in FIG. 3, a sense amplifier is provided for each pair of divided bit lines, while an active pull-up circuit is provided not for each pair of divided bit lines but for each pair of folded bit lines. Therefore, since the potential on an entire bit line of each pair of folded bit lines must be pulled up by a single active pull-up circuit when the active pull-up circuit operates, the active pull-up circuit having large drive capacity is required, and the area of the circuit increases. Additionally, in order to pull up the potential on each of the divided bit lines to the power supply potential V.sub.CC by the active pull-up circuit, the gate potential of a transfer gate transistor, that is, the transfer signal BSC must be boosted over the power supply potential V.sub.CC. However, integration of a memory increases, a gate oxide film of the transfer gate transistor tends to be thinner. For example, the gate oxide film in a 1 Mega-bit dynamic RAM is approximately 200 to 300 .ANG. in thickness. Therefore, if the gate potential is boosted over the power supply potential V.sub.CC, reliability of the gate oxide film is deteriorated. The other prior art showing the above described memory with a folded bit line structure, in which a bit line is divided, each pair of the divided bit lines being provided with a sense amplifier is disclosed in Japanese Patent Publication Gazette No. 57159/1985, by P. V. Basse, entitled "MOS Semiconductor Memory". This document corresponds to DEP No. 2647394.9 of West Germany application.